fault test generation

基本解释

Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文对VLSI测试中的两个主要问题—故障模拟和测试产生进行了深入的分析和研究。
This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
详细分析了固定故障所反映出的状态变换特征，提出状态变换故障模型以及相对应的测试生成压缩方法；
Delay test of microprocessor faces more and more problems with the development of semiconductor technology . Instructioin-based delay fault test generation is a promising approach.
随着半导体工艺的发展，微处理器的时延测试面临着越来越多的问题，基于指令集的处理器时延测试产生是一种很好的尝试方法。